In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
Metrics
Affected Vendors & Products
| Vendors | Products |
|---|---|
| Arm |
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References
| Link | Providers |
|---|---|
| https://developer.arm.com/documentation/111546 |
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History
Thu, 15 Jan 2026 21:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Metrics |
cvssV3_1
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Thu, 15 Jan 2026 08:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| First Time appeared |
Arm
Arm c1-premium Arm c1-ultra Arm cortex-a710 Arm cortex-x2 Arm cortex-x3 Arm cortex-x4 Arm cortex-x925 Arm neoverse-v2 Arm neoverse-v3 Arm neoverse-v3ae Arm neoverse N2 |
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| Vendors & Products |
Arm
Arm c1-premium Arm c1-ultra Arm cortex-a710 Arm cortex-x2 Arm cortex-x3 Arm cortex-x4 Arm cortex-x925 Arm neoverse-v2 Arm neoverse-v3 Arm neoverse-v3ae Arm neoverse N2 |
Wed, 14 Jan 2026 11:15:00 +0000
| Type | Values Removed | Values Added |
|---|---|---|
| Description | In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI. | |
| Weaknesses | CWE-226 | |
| References |
|
MITRE
Status: PUBLISHED
Assigner: Arm
Published: 2026-01-14T10:58:44.342Z
Updated: 2026-01-15T20:46:07.810Z
Reserved: 2025-01-22T14:26:41.767Z
Link: CVE-2025-0647
Vulnrichment
Updated: 2026-01-15T20:45:54.849Z
NVD
Status : Awaiting Analysis
Published: 2026-01-14T11:15:50.027
Modified: 2026-01-15T21:16:02.100
Link: CVE-2025-0647
Redhat
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